SmartSim is a free and open source digital logic circuit design and simulation package.
SmartSim lets you create complex circuits by allowing you to create your own custom components and including them in other circuits, as if they were any other built-in component. These larger circuits can then also be included in other designs as sub-components. SmartSim also offers the ability to print out or export your circuit designs to PDF, PNG, or SVG.
When you have finished designing your circuit, SmartSim offers an interactive simulation feature, allowing you to control your circuit and explore inside sub-components whilst the circuit is running. SmartSim also allows you to produce logic timing diagrams from your simulation’s activity, which can then be exported to PDF, PNG, and SVG formats.
SmartSim was developed by Ashley Newson, and is released under the GNU General Public License Version 3.